As integrated semiconductor circuits, such as dynamic random access memory cells, increase in density in a semiconductor chip, the active power used in a chip containing the memory also increases. A number of different methods have been tried or proposed to minimize the use of active power, i.e., the power used during the writing or reading of memory cells, e.g., by the use of precharged bit line voltages having magnitudes of one half of the chip power supply voltage, known as 1/2 Vdd or 1/2 Vcc, and/or by segmenting the array powered during active cycles, i.e., during the memory reading or writing cycles. Such methods have found acceptance in that they have been able to limit the active power to within the range of about 300 to 400 milliwatts. However, with the density of memory cells on a chip increasing to sixteen million or more, the space required on the chip for necessary multiplexed addresses is not adequate to limit the active power in the desired or acceptable range without segmenting the memory array to a point wherein there results a loss of density.
In order to limit the active power in memories using chips with sixteen million or more cells or bits of stored information, it has been proposed to alter the addressing of the memory chips by using a 12/10 addressing technique rather than the usual 11/11 addressing technique, i.e., to multiplex in twelve addresses during row enable (RE) or row address strobe (RAS) time and to multiplex in ten addresses during the column enable (CE) or column address strobe (CAS) time rather than to multiplex in eleven addresses during the RE time and eleven addresses during the CE time. The 12/10 addressing technique has been found to lower the active power without sacrificing chip density. However, it should be noted that although the 12/10 addressing technique reduces active power, it does require a memory cell refresh rate of 4,000 addresses instead of 2,000 addresses or double the refresh power generally needed to maintain the contents of the memory cells valid. As an example, a standard 16 megabit DRAM using the 11/11 addressing technique has 2,000 refresh cycles every 32 millisecond for an average of 15.7 microseconds between refresh cycles providing a memory availability of 99.3%, whereas a standard 16 megabit DRAM using the 12/10 addressing technique requires 4,000 refresh cycles which lowers the memory availability to 98.7%.
It should also be noted that for smaller systems, i.e., for systems which do not have a large amount of memory, the increase in refresh power is insignificant due to the fact that the majority of the memory chips are frequently active, but they do experience a loss of availability when the 4,000 refresh cycles are required. In memory systems that incorporate battery backup or low power mode, the increase in, i.e., doubling, the refresh power consequently increases the demand on such a power system. In large systems, i.e., wherein many memory chips are provided, the memory is used in banks with only a few chips active at any given time, with the remainder of the memory in standby. With a majority of the chips in standby, the refresh power increase has a major impact on the memory system, particularly to the card which supports modules containing the memories. Another method for alleviating this power problem is to increase, e.g., double, the memory cell retention time by either taking a yield loss or by improving the semiconductor integrated circuit technology, which at present is very expensive.
In U.S. Pat. No 4,831,597, filed on Nov. 9, 1987, by T. Fuse, there is disclosed a memory system wherein bit lines of the memory are selected at a first timing by a row address signal and word lines are selected at a second timing following the first timing by a column address signal of multiplex address signals.
U S. Pat. No. 4,763,302, filed on Apr. 22, 1986, by T. Yamada, discloses a memory system wherein the cells of the array of the memory system can be accessed according to two addressing configurations.